When selecting compensation component values for closed loop voltage regulators there is usually a compromise between values that allow good response to load step changes and values that allow good response to reference voltage changes. That is, component values that provide a fast settling response to load current step changes may cause unacceptable overshoot levels when the voltage reference, and therefore, output voltage, is changed to a new value.
FIG. 1 shows the schematic of a typical closed loop pulse width modulated DC-DC converter 100. In operation, a reference voltage, VREF, is applied to the non-inverting input of an error amplifier, A1. The output of A1, node COMP, drives a pulse width modulator, PWM 125, whose output, PWMOUT, is filtered by LF and CF and becomes the converter's output voltage, VOUT, across the load RL.
VOUT has a relationship to the voltage at node COMP, usually a gain >1, arbitrarily designated as K1, plus generally some voltage offset. VOUT is fed back to a node shown as FB, which is common to the inverting input of A1, through feedback network 110 shown in FIG. 1 as resistor RFB. Another feedback network, 120, shown with a box defined by dashed lines, is employed between node FB and node COMP of amplifier A1. Feedback network 120 shown in FIG. 1 comprises R1, C1, CHF. Feedback networks 110 and 120 set the stability and other operating characteristics of converter 100. Generally, CHF is a much higher impedance than C1, and can be ignored when typical operation of circuit 100 is analyzed.
In the steady state, amplifier A1 drives the COMP node to VCOMP, and consequently VOUT, so that the voltage at node FB (VFB) is equal to VREF. Except for transient effects, VOUT equals VREF and VFB is equal to VREF. A particular PWM circuit might be best compensated for load current changes with values of R1 and C1 having a relatively long RC time constant.
However, a long RC time constant generally produces an unacceptable overshoot in VOUT when responding to a change in VREF. Referring to FIGS. 1 and 2, if VREF is changed by an amount ΔVREF, A1 will change VCOMP by the amount ΔVCOMP, which in turn drives the PWM, so as to make the desired VOUT and the voltage VFB in the steady state to also change by ΔVREF. Note that, because there is a gain of K1 through PWM 125 and the low pass filter comprising LF and CF, ΔVCOMP equals ΔVREF/K1. This produces a change in voltage across the series combination of R1 and C1 being the difference between ΔVREF and ΔVREF/K1. If VREF changes by ΔVREF, then voltage across R1−C1 becomes ΔVREF−ΔVREF/K1, or ΔVREF*(1−1/K1). If the impedance of R1 and C1 is designated as Z1, then a current I(R1−C1) is produced that is equal to ΔVREF*(1−1/K1)/Z1.
Referring to FIGS. 1 and 2, if VREF is changed by an amount ΔVREF, A1 will drive the node to VCOMP, which in turn drives the PWM, so as to make the desired VOUT and the voltage VFB in the steady state to also change by ΔVREF. However, because there is a gain of K1 through PWM 125 and the low pass filter comprising LF and CF, VCOMP only changes by ΔVREF/K1. This produces a voltage across the series combination of R1 and C1 being the difference being between the VFB and the VCOMP. If VREF changes by ΔVREF, then voltage across R1−C1 becomes ΔVREF−ΔVREF/K1, or ΔVREF*(1−1/K1). If the impedance of R1 and C1 is designated as Z1, then a current I(R1−C1) is produced that is equal to ΔVREF*(1−1/K1)/Z1.
I(R1−C1) occurs at the FB node. There is no other path associated with the FB node for this current to flow except from VOUT through feedback resistor RFB. A voltage drop will therefore result across RFB, making the actual VOUT mismatch VFB, resulting in a mismatch of VOUT with VREF.
FIG. 2 shows the simulated response of various nodes of converter 100 when R1, C1 provides a relatively long time constant network resulting from a change in VREF=ΔVREF. As noted above, due to gain K1 through PWM 125 and the low pass filter comprising LF and CF, VCOMP<VREF. As a result, I(R1−C1) is seen. This current results in the actual VOUT being seen to not closely track VREF (which is equal to the Desired VOUT). This results in the undesirable overshoot shown in VOUT for a change in VREF, which generally forces a compromise in the component values, such as a reduction in the R1C1 time constant. However, as noted above, a reduction in the R1C1 time constant degrades the response of circuit 100 to load step changes. What is needed is a pulse width modulated converter design that allows selection of compensation component values that removes the tradeoff in performance between response to changes in load steps and response to reference voltage changes.